Workshop on heterogeneous and reconfigurable architectures for the future of computing
The forthcoming end of Moore's law encourages us to challenge new approaches for the future of computing. One of the promising approaches is heterogeneous and reconfigurable architecture with reconfigurable devices such as FPGAs and CGRA processors. Many emerging AI accelerators leverage reconfigurability, dataflow, large distributed on-chip memories and domain-specific languages. In this workshop, we discuss opportunities and challenges of heterogeneous and reconfigurable architectures for future computing as well as collaboration opportunities, introducing on-going research projects, especially in the internatinoal activity of JLESC, regarding FPGAs and other reconfigurable architectures and applications.
Kentaro Sano, Tomohiro Ueno (RIKEN);
Kazutomo Yoshii (Argonne National Laboratory);
Carlos Alvarez Martinez, Juan Miguel de Haro (Barcelona Supercomputing Center)