RISC-V is inevitable

RISC-V has grown from a university project into a global open standard with a thriving ecosystem comprising hundreds of collaborating organizations, including most of the major companies in computing. This talk will describe how RISC-V is inevitable across all of computing, displacing legacy proprietary instruction sets.

Also, as the inventors of RISC-V and performance density leaders, we would like to introduce SiFive’s new P600 and P400 series of RISC-V processors, which are perfectly tuned to offer the best power and performance efficiency and compute density for next generation wearables, the smart home, industrial automation, and other consumer devices.

Presenters

An Introduction to the Open FPGA Stack

A major barrier to FPGA adoption, even in applications where an FPGA-based solution is the most optimal in terms of power and performance, is accessibility to a larger number of developers. Given the complexities of modern FPGA designs, rarely is a single development team responsible for all the IP and software required to perform a solution. In order to achieve productivity scale, a common means to integrate various IP solutions both in hardware and software is desired. 

The Open FPGA Stack (OFS) is a complete hardware and software infrastructure that is fully open-sourced and comprises composable hardware code and upstreamed kernel code to kernel.org to enable a collaborative community of FPGA developers. This includes IP developers, board vendors, and software service providers.